Advancements in computing technology and a need for greater data management have led to an increase in fabrication of SoC integrated circuits. SoCs typically integrate several components of a computer on a single chip substrate. Specifically, SoCs integrate analog, mixed-signal, digital and/or radio frequency circuitry on a single chip substrate, and can increase processing power by using multiple processors and an on-chip interconnection.
Requests associated with data processing often require instructions to be obtained from memory for use by a processor (or, in the case of multi-processors, for use by a central processing unit (CPU) core of a multi-processor). However, obtaining instructions or other data from main memory can introduce excess latency.
In some cases, SoC design includes multi-level cache memory architectures composed of one or more per processor (or CPU core) cache memories and one or more shared processor (or shared CPU core) cache memories. Shared CPU core cache memories are shared and accessible by two or more processors, or, in multi-processor embodiments, shared and accessible by two or more CPU cores. Unfortunately, notwithstanding the advantages of multi-level cache memory architectures, the result of these types of architectures is often high-complexity. Accordingly, systems and methods of low complexity that facilitate reduced latency employing multi-level cache memory architectures are desired.
The above information is merely intended to provide a contextual overview of aspects of SoCs having multi-level cache memories and is not intended to be exhaustive.